1. Field of the Invention
This invention relates generally to the field of programmable logic devices, and more particularly to programmable logic devices providing product term signals at its outputs.
2. Description of the Prior Art
Various types of programmable logic devices are known in the prior art. Referring to FIG. 1, a first type of programmable logic device 1 known in the prior art is illustrated, and is generically referred to as a PLA (programmable logic array). Referring to FIG. 1, programmable logic array 1 is comprised of a programmable AND array 2, shown in simplified form as having logical inputs A, A and B, B as the inputs to the programmable AND array. Included within programmable AND array 2 are a plurality of programmable logic elements, which may be, for example, nonvolatile memory cells, for selectively connecting the logical input signals provided on lines 3, 4, 5 and 6 to array lines (not shown) in programmable AND array 2. Based on the programmed or unprogrammed state of cells at the intersection between the array lines of the AND array and the product term lines (illustrated in FIG. 1 as PT0, PT1, PT2, and PT3) and the logical signals provided to the inputs of programmable AND array 2, product term output signals are provided on product term lines. The outputs from programmable AND array 2 are provided over lines PT0-PT3 as inputs to programmable OR array 7. In programmable logic array 1, both programmable AND array 2 and programmable OR array 7 are fully programmable, meaning any one of the inputs to either array may be connected to any one of its outputs. The outputs from programmable OR array 7 are indicated at 8, 9, 10 and 11. It is at these outputs that the logical result is provided based upon the inputs A, A and B, B and the programmed state of programmable AND array 2 and programmable OR array 7. Although programmable logic array 1 is very flexible due to its high connectability, it suffers from the disadvantage of speed and the requirement of a larger die size over other types of programmable logic devices.
A second type of prior art programmable logic device is illustrated in FIG. 2. Programmable logic device 15 illustrated in FIG. 2 is generally referred to as a PAL device. PAL device 15 is comprised of a programmable AND array 16, which is shown in simplified form, and includes array lines (not shown) for receiving logical input signals A, A and B B. Based on the programmed/unprogrammed state of devices in programmable AND array 16, product term output signals are provided on product term lines PT0, PT1, PT2, and PT3. Product term signals provided over these lines are inputs to fixed OR gates 17 and 18, and the resulting logical output is provided at terminals 19 and 20. It will of course be appreciated that the logical outputs at terminals 19 and 20 are a function of the programmed/unprogrammed state of the cells in programmable AND array 16 and the result of ORing those signals by fixed OR gates 17 and 18. PAL device 15, although faster than PLA device 1, has less flexibility in terms of the logical results obtainable since the product term outputs from programmable AND array 16 are dedicated to predetermined OR gates.